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3-1826 august 1997 hi7131, hi7133 3 1 / 2 digit, low power, high cmrr, lcd/led display-type a/d converters features ? 120db cmrr equal to 0.01 count/v of common mode voltage error ? fast recovery from input overrange results correct first-reading after overload ? guaranteed 0000 reading for 0v input ? true polarity at zero for precise null detection ? 1pa input current (typ) ? true differential input and reference ? single or dual supply operation capability ? direct lcd display drive - hi7131 ? direct led display drive - hi7133 ? low noise, 15 m v p-p without hysteresis or overrange hangover ? low power dissipation, guaranteed less than 1mw, results 8000 hours (typ) 9v battery life ? no additional active components required applications ? handheld instruments ? basic measurements: voltage, current, resistance pressure, temperature, fluid flow and level, ph, weight, light intensity ? dmms and dpms description the intersil hi7131 and hi7133 are 3 1 / 2 digit, a/d convert- ers that have been optimized for superior dc common mode rejection (cmrr) when used with a split 5v supply or a single 9v battery. the hi7131 contains all the neces- sary active components on a single ic to directly interface an lcd (liquid crystal display). the supply current is under 100 m a and is ideally suited for battery operation. the hi7133 contains all the necessary active components on a single ic to directly interface an led (light emitting diode). the hi7131 and hi7133 feature high accuracy performance like, 120db of cmrr, auto-zero to less than 10 m v of offset, fast recovery from over load, zero drift of less than 1 m v/ o c, input bias current of 10pa maximum, and rollover error of less than one count. a true differential signal and reference inputs are useful features in all systems, but gives the designer an advantage when measuring load cells, strain gauges and other bridge-type transducers. the hi7131 and hi7133 are supplied in a 40 lead plastic dip and a 44 lead metric plastic quad ?atpack package. ordering information part no. temp. range ( o c) package pkg. no. hi7131cpl 0 to 70 40 ld pdip e40.6 hi7131cm44 0 to 70 44 ld mqfp q44.10x10 hi7133cpl 0 to 70 40 ld pdip e40.6 HI7133CM44 0 to 70 44 ld mqfp q44.10x10 file number 3373.2 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. http://www.intersil.com or 407-727-9207 | copyright ? intersil corporation 1999
3-1827 hi7131, hi7133 pinouts hi7131cpl, hi7133cpl (pdip) top view hi7131cm44, HI7133CM44 (mqfp) top view 13 1 2 3 4 5 6 7 8 9 10 11 12 14 15 16 17 18 19 20 v+ d1 c1 b1 a1 f1 g1 e1 d2 c2 b2 a2 f2 e2 d3 b3 f3 e3 (1000) ab4 (minus) pol 28 40 39 38 37 36 35 34 33 32 31 30 29 27 26 25 24 23 22 21 osc 1 osc 2 osc 3 test ref hi ref lo c ref + c ref - common in hi in lo a-z buff int v- g2 (tens) c3 a3 g3 bp/gnd (units) (tens) (100s) (100s) nc nc test osc3 nc osc2 osc1 v+ d1 c1 b1 ref hi ref lo cref+ cref- common in hi in lo a-z buff int v- a1 f1 g1 b1 d2 c2 b2 a2 f2 b2 d3 nc g2 c3 a3 g3 bpgnd pol ab4 e3 f3 b3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 28 27 26 25 24 23 22 21 20 19 18 39 38 37 36 35 34 33 32 31 30 29 44 43 42 41 40
3-1828 figure 89. typical application circuit figure 90. test circuit analog a-z buff int in hi in lo common c ref + v+ osc1 osc2 osc3 c ref - ref hi ref lo v- input lcd/led display 9v 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 v+ d1 c1 b1 a1 f1 g1 e1 d2 c2 b2 a2 f2 e2 d3 b3 f3 e3 ab4 pol g2 c3 a3 g3 bp/gnd 28 40 39 38 37 36 35 34 33 32 31 30 29 27 v- buff osc 1 osc 2 osc 3 test ref hi ref lo c ref + c ref - common in hi in lo a-z int c ref 0.1 m f dut c in c az c int 0.01 m f 0.47 m f 0.047 m f 180k 1m 1 m f external clock external reference external input hi7131, hi7133 lcd/led display and test logic critical components general speci?cations: 1. c int : low dielectric absorption capacitor, polypropylene or similar 2. c az , c ref , c in : low leakage capacitors 1 0.47 m f +5v 0.47 m f -5v c vref r int r in c ref = 0.1 m f c in = 0.01 m f c int = 0.047 m f c az = 0.47 m f c vrh =1 m f r in = 1m w r int = 180k w hi7131, hi7133
3-1829 absolute maximum ratings thermal information supply voltage, v+ to v-. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +15v signal inputs, pin# 30, 31 (note 1). . . . . . . . . . . . . . . . . . . . v+ to v- reference inputs, pin# 35, 36 . . . . . . . . . . . . . . . . . . . . . . . v+ to v- clock input, osc1, pin# 40 (note 2) . . . . . . . . . . . . test pin to v+ all other analog leads, pin# 27-29, 32-34 . . . . . . . . . . . . . v+ to v- all other digital leads, pin# 2-25, 38, 39 (note 2). . . . . . . . . . . . . . . . . . . test pin to v + operating conditions operating temperature, t a . . . . . . . . . . . . . . . . . . . . . . .0 o c to 70 o c thermal resistance (typical, note 3) q ja ( o c/w) pdip package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mqfp package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . . 150 o c maximum storage temperature range . . . . . . . . . .-65 o c to 150 o c maximum lead temperature, pdip package (soldering 10s) 300 o c (mqfp - lead tips only) caution: stresses above those listed in absolute maximum ratings may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this speci?cation is not im plied. notes: 1. input voltages may exceed the supply voltages provided the input current is limited to 100 m a. 2. test pin is connected to internally generated digital ground through a 500 w resistor (see text for test pin description). 3. q ja is measured with the component mounted on an evaluation pc board in free air. electrical speci?cations (notes 5, 6, 7) t a = 25 o c. device is tested in the circuit shown in figure 2. full scale range (fsr) = 200.0mv, unless otherwise speci?ed parameter test conditions min typ max units accuracy zero input reading v in = 0v -000 000 +000 reading ratiometric reading v in hi = v ref hi , v in lo = v ref lo = v common v ref hi - v ref lo = 100mv 999 999/ 1000 1001 reading rollover error v in = 199mv - 0.2 1 count linearity error fsr = 200mv or 2v (notes 5, 8) - 0.2 1 count zero input reading drift v in = 0v over full temperature range (notes 5, 8) - 0.2 1 0.01 m v/ o c count/ o c scale factor temperature coefficient v in = 199mv, over full temperature range, reference drift not included (notes 5, 8) - 1 5 0.01 ppm/ o c count/ o c equivalent input noise (peak-to-peak value not exceeded 95% of the time) v in = 0v (notes 5, 8) - 15 0.15 - m v count input common mode voltage sensitivity v cm = 1v, v in = 0v (notes 5, 6, 8, 9) - - 1 0.01 m v/v count/v input leakage current v in = 0v (notes 5, 8) - 1 10 pa overload recovery period v in changing from 10v to 0v (notes 5, 8) - - 1 conversion cycle common pin common pin voltage (with respect to v+, i.e., v+ - v common ) v+ to v- = 10v 2.4 2.8 3.2 v common pin voltage temperature coefficient v+ to v- = 10v (notes 5, 8) - 150 - ppm/ o c common pin sink current +0.1v change on v common (note 5) - 3 - ma common pin source current -0.1v change on v common (note 5) - 1 - m a hi7131, hi7133
3-1830 display driver (hi7131) peak-to-peak segment drive voltage v+ to v- = 10v 4 5 6 v peak-to-peak backplane drive volt- age 456 v power supply (nominal supply voltage; v+ to v- = 10v) supply current (does not include common pin current) v in = 0v (note 10) oscillator frequency = 16khz - 70 100 m a power dissipation capacitance vs clock frequency (notes 5, 8) - 40 - pf display driver (hi7133) segment sink current (except pins 19 and 20) v+ = +5.0v driver pin voltage = 3.0v 5 8.5 - ma pin 19 sink current 10 16 - ma pin 20 sink current 47 - ma power supply nominal supply voltage; v+ = +5v, v- = -5v, both respect to gnd pin v+ supply current (note 10) v in = 0v oscillator frequency = 16khz does not include common pin and display current - 70 100 m a v- supply current (notes 5, 10) - 40 - m a power dissipation capacitance versus clock frequency (notes 5, 8) - 40 - pf notes: 4. dissipation rating assumes device is mounted with all leads soldered to printed circuit board. 5. all typical values have been characterized but not tested. 6. see parameters definition section. 7. count is equal to one number change in the least significant digit of the display. 8. parameter not tested on a production basis, guaranteed by design and/or characterization. 9. see differential input section. 10. 48khz oscillator increases current by 20 m a (typ). electrical speci?cations (notes 5, 6, 7) t a = 25 o c. device is tested in the circuit shown in figure 2. full scale range (fsr) = 200.0mv, unless otherwise speci?ed (continued) parameter test conditions min typ max units hi7131, hi7133
3-1831 typical integrator ampli?er output waveform (int pin) design information summary sheet ? oscillator frequency f osc ? 0.45/rc (osc) c osc 3 50pf r osc > 50k w c osc = 50pf, r osc = 180k w ; f osc (typ) = 48khz ? clock frequency f clock = f osc /4 ? clock period t clock = 1/f clock ? conversion cycle t cyc = 4000 x t clock = 16000 x t osc for f osc = 40khz; t cyc = 400ms ? signal integration period t int = 1000 x t clock ? 60/50hz rejection criteria t int / t 60hz or t int / t 50hz = integer ? optimum full scale analog input range v infs = 200mv to 2v ? inputs voltage range (v- + 1v) < v in lo or v in hi < (v+ - 1v) ? maximum integration current i int(max) = v infs / r int maximum integration current should be the maximum buffer output current with no nonlinearity effect. maximum buffer output current = 1 m a ? integrator maximum output voltage swing v int(max) = (t int ) (i int(max) )/c int (v- + 0.5) < v int(max) < (v+ - 0.5) (typ) v int(max) = 2v ? integrating resistor r int = v infs / i int(max) ? integrating capacitor c int = (t int ) (i int(max) ) / v int(max) ? auto-zero capacitor value reference capacitor value 0.1 m f < c ref < 1 m f ? reference inputs voltage range v- < v reflo or v refhi < v+ ? reference voltage v ref = v infs /2 ? common pin voltage v common = v+ - 2.8, (typ), v common is regulated and can be used as a reference. it is biased between v+ and v- and regulation is lost at (v+ -v-) < 6.8v. v common pin does not have sink capability and can be externally pulled down to lower voltages. ? display type lcd, non-multiplexed ? power supply, v+ to v- single +9v or 5v nominal, +5v to +12v functional ? display reading reading = 1000 x (v in / v ref ) maximum reading = 1999, for v in = 1.999 x v ref integrator voltage swing auto-zero phase 100 counts or 990 - 2990 counts signal integrate phase fixed 1000 counts deintegrate phase 0 - 2000 counts zero integrate phase 10 counts or 900 counts 4000 counts: total of each conversion cycle note: 1 count = 1 clock cycle = 4 oscillator cycles. hi7131, hi7133
3-1832 pin descriptions pin number name function description 40 pin dip 44 pin flatpack 1 8 v+ supply power supply. 2 9 d1 output driver pin for segment d of the display units digit. 3 10 c1 output driver pin for segment c of the display units digit. 4 11 b1 output driver pin for segment b of the display units digit. 5 12 a1 output driver pin for segment a of the display units digit. 6 13 f1 output driver pin for segment f of the display units digit. 7 14 g1 output driver pin for segment g of the display units digit. 8 15 e1 output driver pin for segment e of the display units digit. 9 16 d2 output driver pin for segment d of the display tens digit. 10 17 c2 output driver pin for segment c of the display tens digit. 11 18 b2 output driver pin for segment b of the display tens digit. 12 19 a2 output driver pin for segment a of the display tens digit. 13 20 f2 output driver pin for segment f of the display tens digit. 14 21 e2 output driver pin for segment e of the display tens digit. 15 22 d3 output driver pin for segment d of the display hundreds digit. 16 23 b3 output driver pin for segment b of the display hundreds digit. 17 24 f3 output driver pin for segment f of the display hundreds digit. 18 25 e3 output driver pin for segment e of the display hundreds digit. 19 26 ab4 output driver pin for both a and b segments of the display thousands digit. 20 27 pol output driver pin for the negative sign of the display. 21 28 bp/gnd output driver pin for the lcd backplane/power supply ground. 22 29 g3 output driver pin for segment g of the display hundreds digit. 23 30 a3 output driver pin for segment a of the display hundreds digit. 24 31 c3 output driver pin for segment c of the display hundreds digit. 25 32 g2 output driver pin for segment g of the display tens digit. 26 34 v- supply negative power supply. 27 35 int output integrator amplifier output. to be connected to integrating capacitor. 28 36 buff output input buffer amplifier output. to be connected to integrating resistor. 29 37 a-z input integrator amplifier input. to be connected to auto-zero capacitor. 30 31 38 39 in lo in hi input differential inputs. to be connected to input voltage to be measured. lo and hi designators are for reference and do not imply that lo should be connected to lower potential, e.g., for negative inputs in lo has a higher potential than in hi. 32 40 common supply/ output internal voltage reference output. 33 34 41 42 c ref - c ref + connection pins for reference capacitor. 35 36 43 44 ref lo ref hi input input pins for reference voltage to the device. ref hi should be positive reference to ref lo. 37 3 test input display test. turns on all segments when tied to v+. 38 39 40 4 6 7 osc3 osc2 osc1 output output input device clock generator circuit connection pins. hi7131, hi7133
3-1833 de?nition of speci?cations count a count is equal to one number change in the least signi?- cant digit of the display. the analog size of a count referred to adc input is: max reading +1 for a 3 1 / 2 digit display is 2000 (1999+1). zero input reading the reading of the adc display when input voltage is zero and there is no common mode voltage, i.e., the inputs are shorted to common pin. ratiometric reading the reading of the adc display when input voltage is equal to reference voltage, i.e., in hi tied to ref hi and in lo tied to ref lo and common pins. the accuracy of reference voltage is not important for this test. rollover error difference in the absolute value reading of adc display for equal magnitude but opposite polarity inputs. the input volt- age should be close to full scale, which is the worst case condition. linearity deviation of the adc transfer function (output reading versus input voltage transfer plot) from the best straight line ?tted to adc transfer plot. scale factor temperature coef?cient the rate of change of the slope of adc transfer function due to the change of temperature. equivalent input noise the total random uncertainty of the adc for converting a ?xed input value to an output reading. this uncertainty is referred to input as a noise source which produces the equivalent effect. it is given for zero input and is expressed as peak-to-peak noise value and submultiples of counts. overload recovery period a measure of how fast the adc will display an accurate reading when input changes from an overload condition to a value within the range. this is given as the number of con- version cycles required after the input goes within the range. theory of operation the hi7131 and hi7133 are dual-slope integrating type a/d converters. as the name implies, its output represents the integral or average of the input signal. a basic block diagram of a dual-slope integrating converter is shown in figure 3. a conventional conversion cycle has two distinct phases: first, the input signal is integrated for a ?xed interval of time. this is called the signal integration phase. in this phase, the input of the integrator is connected to the input signal through the switch. during this time, charge builds up on c int , which is proportional to the input voltage. the next phase is to discharge c int . this is called reference integration or deintegration phase, with the use of a ?xed ref- erence voltage. the time it takes to discharge the c int is directly proportional to the input signal. this time is con- verted to a digital readout by means of a bcd counter, driven by a clock oscillator. during this phase, the integrator input is connected to an opposite polarity reference voltage through the switch to discharge c int . notice that during the integration phase, the rate of charge built up on the capacitor is proportional to the level of the input signal, and there is a ?xed period of time to integrate the input. however, during the discharge cycle the rate of discharge is ?xed and there is a variable time period for com- plete discharge. a 3 1 / 2 digit bcd counter is shown in the block diagram, the period of integration is determined by 1000 counts of this counter. just prior to a measurement, the counter is reset to zero and c int has no charge. at the beginning of the mea- surement, the control logic enables the counter and the inte- grator input is connected to the input node. charge begins accumulating on c int and the output of the integrator moves down or up respectively for positive or negative inputs. this process continues until the counter reaches 1000 counts. this will signal the control logic for the start of the deintegrat- ing cycle. the control logic resets the counter and connects the integrator input to a reference voltage opposite to that of the input signal. the charge accumulated on c int is now starting to be removed and the counter starts to count up again. as soon as all the charge is removed, the output of the integrator reaches 0v. this is detected by the compara- tor and the control logic is signaled for the end of a measure- ment cycle. at this time the number accumulated in the counter is the representation of the input signal. this number will be stored on the latches and displayed until the end of the next measurement cycle. analog count size full scale range max reading 1 + --------------------------------------------- , = hi7131, hi7133
3-1834 figure 3 shows a typical waveform of the integrator output for 2 different positive input values and the associated repre- sentation of the counter output for those inputs. t int is the time period of integrating phase. t 1 and t 2 are the end of measurement for 2 different inputs. the dual slope integrating technique puts the primary responsibility for accuracy on the reference voltage. the val- ues of r int and c int and the clock frequency (f clk ) are not important, provided they are stable during each conversion cycle. this can be expressed mathematically as follows: it can be seen that the output reading of the adc is only proportional to the ratio of v in over v ref . the last equation also demonstrates that for the maximum display reading (i.e., 1999) we will have v in = 1.999 v ref . this implies that in this con?guration the full scale range of the converter is twice its reference voltage. the inherent advantages of integrating a/d converters are; very small nonlinearity error, no possibility of missing codes and good high frequency noise rejection. furthermore, the integrating converter has extremely high normal mode rejection of frequencies whose periods are an integral multiple of the integrating period (t int ). this feature can be used to reject the line frequency related noises which are riding on input voltage by appropriate selection of clock frequency. this is shown in figure 4. v in +v ref -v ref reference voltage 3 1 / 2 digit bcd counter maximum count: 1999 reset enable clk control logic clock generator latches and display drivers latch display integrator comparator f clk r int switch drive timing signals - + - + c int 0 t int t 1 t 2 t t counter output integrator output for positive input variable slope fixed slope variable deintegration time fixed integration time 1000 figure 91. dual slope integrating a/d converter d v int 1 r int c int --------------------------- - v in dt 0 t int 1 r int c int --------------------------- - v ref dt 0 t deint == d v int v in t int r int c int --------------------------- - v ref t deint r int c int ---------------------------------- - == v in : input average value during integration time t int 1000 1 f clk ------------ ? ?? = t deint a ccumulated counts 1 f clk ------------ ? ?? = accumulated counts 1000 v in v ref --------------- display reading == 30 20 10 0 0.1/t int 1/t int 10/t int f noise rejection, (db) t int = integration period f = input or noise frequency figure 92. noise rejection for integrating type a/d converter hi7131, hi7133
3-1835 hi7131/33 vs icl7136/37 figure 5 shows the analog front end block diagram of both hi7131/33 and icl7136/37. the difference is the common reference voltage generator connection and 2 extra analog switches in the icl7136. the hi7131 architecture uses the inlo as the reference point of the integrator (non-inverting input of the integrator ampli?er) in all the phases of the con- version cycle. the icl7136 uses inlo as a reference point only during integration cycle and common pin is used as the integrator reference point during auto-zero, deintegrate, and zero integrate phases. the circuit con?guration of the hi7131 results in a superior 120db rejection of dc common mode on the inputs. how- ever, the hi7131 has reduced ac common mode noise rejection, since the noise on the inlo input can cause errors during the deintegration phase. the circuit con?guration of the icl7136 is unaffected by the ac noise riding on the inputs, but the dc common mode rejection on the input is only 86db. figure 93a. hi7131 and hi7133 analog section functional diagram figure 93b. icl7136 and icl7137 analog section functional diagram figure 93. hi7131, hi7133 vs icl7136, icl7137 analog sections de- de+ v common generator polarity flip-flop zero crossing detector v - 26 c int c az r int buff a-z int v+ az comparator inhi common inlo 31 32 30 de- de+ int az 34 c ref + 36 refhi c ref reflo 35 az and zi az and zi zi input high 33 c ref - 28 29 27 v+ to digital section v- integrator 1 - + - + - + de- de+ v common generator polarity flip-flop zero crossing detector v - 26 c int c az r int buff a-z int v+ - + az comparator inhi common inlo 31 32 30 de- de+ int az 34 c ref + 36 refhi c ref reflo 35 az and zi az and zi zi input high 33 c ref - 28 29 27 v+ to digital section az and de and zi v- integrator 1 - + - + hi7131, hi7133
3-1836 analog section description figure 5a shows a simpli?ed diagram of the analog section of the hi7131 and hi7133. the circuit performs basic phases of dual slope integration. furthermore, the device incorporates 2 additional phases called auto-zero and zero integrate. the device accepts differential input signals and reference voltages. also, there is a reference voltage generator which sets the common pin 2.8v below the v+ supply. a complete conversion cycle is divided into the following four phases: 1. auto-zero (a/z) 2. signal integrate (int) 3. deintegrate or reference integrate (de ) 4. zero integrate (zi) digitally controlled analog switches direct the appropriate signals for each phase of the conversion. auto-zero phase during auto-zero three things occur. first, in hi is discon- nected from the device internal circuitry and internally shorted to in lo. second, the reference capacitor is charged to the reference voltage. third, a feedback loop is closed around the system to charge the auto-zero capacitor c az and integrating capacitor c int to compensate for offset voltages in the buffer ampli?er, integrator, and comparator. since the comparator is included in the loop, the a/z accu- racy is limited only by the noise of the system. in any case, the offset referred to the input is less than 10 m v. signal integrate phase during signal integrate the auto-zero loop is opened and the internal input high is connected to the external pins. the converter then integrates the differential voltage between in hi and in lo for a ?xed time. this differential voltage can be within a wide input common mode range: up to 1v from either supply. at the end of this phase, the polarity of the integrated signal is determined. deintegrate phase during this phase the in lo and the internal input high are connected across the previously charged reference capacitor. the bridge type circuitry within the chip ensures that the capacitor will be connected with the correct polarity to cause the integrator output to return to zero. the time required for the output to return to zero is proportional to the input signal. as speci?ed before, the digital reading displayed is: . zero integrate phase this phase is provided to eliminate overrange hangover and causes fast recovery from heavy overrange. during this phase a feedback loop is closed around the system by connecting comparator output to internal input high. this will discharge the integrator capacitor (c int ), causing the integrator output return to zero. during this phase the refer- ence capacitor is also connected to reference input, charg- ing to the reference voltage. a typical integrator output voltage during different phases is shown on the design information summary sheet. this integrator output is for negative inputs and is referred to in lo. for positive inputs the integrator output will go negative. digital section description figure 6 shows the block diagram of the digital section of the hi7131. the diagram shows the clock generator, control logic, counters, latches and display decoder drivers. an internal digital ground is generated from a 6v zener diode and a large p-channel source follower. this supply is capa- ble of absorbing the relatively large capacitive currents when the lcd backplane (bp) and segment drivers are switched. display drivers a typical segment output driver consists of p-channel and n-channel mosfets. an lcd consists of a backplane (bp) and segments. bp covers the whole area under the segments. because of the nature of the lcds, they should be driven by square waves. the bp frequency is the clock frequency divided by 800. for three readings/second this is a 60hz square-wave with a nominal amplitude of 5v. the segments are driven at the same frequency and amplitude and are in phase with bp when off, but out of phase when on. in all cases negligible dc voltage exists across the segments. the polarity indica- tion is on for negative analog inputs. if in lo and in hi are reversed, this indication can be reversed also, if desired. the hi7131 is a direct display drive (versus multiplexed) and each segment in each digit has its own segment driver. the display font and the segment assignment on the display are also shown in figure 6. figure 6 shows the block diagram of the digital section of the hi7133. the diagram shows the clock generator, control logic, counters, latches and display decoder drivers. the supply rails of the digital circuitry are v+ and gnd. display drivers a typical segment output consists of a p-channel and an n-channel mosfet. this con?guration is designed to drive common anode led displays. the nominal sink current for each segment is 8ma, a typical value for instrument size common anode led displays. the driver for the thousand digit is twice as big as other segments and can sink 16ma since it is actually driving 2 segments. the sink current for the polarity driver is 7ma. the polarity driver is on for negative inputs. the hi7133 is a direct display drive (versus multiplexed) and each segment in each digit has its own seg- ment driver. the display font and the segment assignment on the display are also shown in figure 7. clock generator the clock generator circuit basically includes 2 cmos inverters and a divide-by-4 counter. it is designed to be used in 2 different basic con?gurations. digita l reading 1000 v inhi v inlo C v refhi v reflo C -------------------------------------------------- ? ? ?? = hi7131, hi7133
3-1837 7 segment decode segment output 0.5ma 2.0ma internal digital ground typical segment output v+ lcd phase driver latch 7 segment decode ? 200 logic control internal v th = 1v 7 segment decode 1000s 100s 10s 1s to switch drivers from comparator output digital ground +4 polarity clock ? 40 39 38 osc 1 osc 2 osc 3 backplane 21 v+ test v- 500 w 37 26 6.2v ? three inverters one inverter shown for clarity counter counter counter counter c a b c d f g e a b a b c d f g e a b c d f g e hi7131 to segment 0.5ma 8ma gnd typical segment output v + 7 segment decode logic control 7 segment decode 1000s 100s 10s units to switch drivers from comparator output +4 polarity clock 40 39 38 osc 1 osc 2 osc 3 test 500 w 21 counter counter counter counter 37 gnd latch 7 segment decode ? c a b c d f g e a b a b c d f g e a b c d f g e hi7133 ? three inverters one inverter shown for clarity figure 94. digital section hi7131, hi7133
3-1838 1. figure 7a, an external oscillator driving osc 1. 2. figure 7b, an rc oscillator using all 3 oscillator circuit pins. the oscillator output frequency is divided by 4 before it clocks the rest of the digital section. notice that there are 2 separate frequencies which are referred to as; oscillator frequency (f osc ) and clock frequency (f clk ) with the relation of: to achieve maximum rejection of 60hz pickup, the signal integrate cycle should be a multiple of 60hz. for 60hz, rejection oscillator frequencies of 120khz, 80khz, 60khz, 48khz, 40khz, 33 1 / 3 khz, etc. should be selected. for 50hz rejection, oscillator frequencies of, 100khz, 66 2 / 3 khz, 50khz, 40khz, etc. would be suitable. note that 40khz (2.5 read- ings/sec) will reject both 50hz and 60hz (also 400hz and 440hz). for the rc oscillator con?guration the relationship between oscillator frequency, r and c values are: (r in ohms and c in farads.) system timing as it has been mentioned, the oscillator output is divided by 4 prior to clocking the digital section and speci?cally, the internal decade counters. the control logic looks at the counter outputs and comparator output (see analog section) to form the appropriate timing for 4 phases of conversion cycle. the total length of a conversion cycle is equal to 4000 counts and is independent of the input signal magnitude or full scale range. each phase of the conversion cycle has the following length: auto-zero phase 100 counts in case an overrange is detected. 990 to 2990 counts for normal conversion. for those inputs which are less than full scale, the deintegrate length is less than 2000 counts. those extra counts on deintegrate phase are assigned to auto-zero phase to keep the conversion cycle constant. signal integrate phase 1000 counts, a ?xed period of time. the time of integration can be calculated as: deintegrate phase 0 to 2000 counts, variable length phase depending on the input voltage. zero integrate phase 10 counts in case of normal conversion. 900 counts in case an overrange is detected. functional considerations of device pins common pin the common pin is the device internal reference generator output. the common pin sets a voltage that is about 2.8v less than the v+ supply rail. this voltage (v+ - v common ) is the on-chip reference which can be used for setting converter reference voltage. within the ic, the common pin is tied to an n-channel tran- sistor capable of sinking up to 3ma of current and still keeping common voltage within the range. however, there is only 1 m a of source current capability. the common pin can be used as a virtual ground in single supply applications when the external analog signals need a reference point in between the supply rails. if higher sink and source current capability is needed for virtual ground a unity gain op-amp can be used as a buffer. differential inputs (in lo, in hi) the input can accept differential voltages anywhere within the common mode range of the input ampli?er, or speci?cally from 1v below the positive supply to 1v above the negative supply. in this range, the system has a cmrr of 120db (typ). however, care must be exercised to assure the integrator output does not saturate. this is illustrated in figure 8, which shows how common mode voltage affects maximum swing on the integrator output. figure 8 shows the circuit con?guration during conversion. in this ?gure, common mode voltage is considered as a voltage on the in lo pin referenced to (v+ - v-) / 2, which is usually the gnd in a dual supply system. clock internal to part 40 39 38 test ? 4 figure 95a. external signal clock internal to part 40 39 38 ? 4 r c figure 95b. rc oscillator figure 95. clock circuits f clk f osc 4 ------------- - = f osc 0.45 r osc c osc --------------------------------- ? t int 1000 1 f clk ------------ ? ?? 4000 1 f osc ------------- - ? ?? . == hi7131, hi7133
3-1839 a worst case condition would be a large positive common- mode voltage with a near full scale negative differential input voltage. the negative input signal drives the integrator posi- tive when most of its swing has been used up by the positive common mode voltage. for these critical applications the integrator output swing can be reduced to less than the rec- ommended 2v full scale swing with little loss of accuracy. the integrator output can swing to within 0.3v of either supply without loss of linearity. differential reference (ref hi, ref lo) and reference capacitor pins (c ref +, c ref -) as was discussed in the analog section (figure 5), the differ- ential reference pins are connected across the reference capacitor (connected to pins c ref + and c ref -) to charge it during the zero integrate and the auto-zero phase. then the reference capacitor is used as either a positive or negative reference during the deintegrate phase. the reference capacitor acts as a ?ying capacitor between the reference voltage and integrator inputs in the deintegrate phase. the common mode voltage range for the reference inputs is v+ to v-. the reference voltage can be generated anywhere within the power supply range of the converter. the main source of rollover error is reference common mode voltage caused by the reference capacitor losing or gaining charge to or from stray capacitance on its nodes. if there is a large common mode voltage, the reference capacitor can gain charge (increase voltage) when called upon to deintegrate a positive signal but lose charge (decrease voltage) when called up to deintegrate a negative input signal. this change in reference for positive or negative input voltage will give a rollover error. however, by selecting the reference capacitor such that it is large enough in comparison to the stray capac- itances, this error can be held to less than 0.5 counts worst case. see the component value selection section for auto-zero capacitor value. test pin the test pin serves two functions. it is coupled to the internally generated digital ground through an effective 500 w resistor. thus, it can be used as the digital ground for external digital circuits such as segment drivers for decimal points or any other annunciator the user may want to include on the lcd display. for these applications the external digital circuit should be supplied between v+ and test pin. figures 9 and 10 show such an application. in figure 9 a mosfet transis- tor is used to invert the bp signal to drive the decimal point. the mosfet can be any general purpose type with a thresh- old voltage less than 3.5v and on resistance less than 500 w . figure 10 uses an cmos ic xor gate to generate controlla- ble decimal point drives. no more than a 1ma load should be applied to test pin by any external digital circuitry. the second function of the test pin is the lamp test. when the test pin is pulled high (to v+) all segments will be turned on and the display should read -1888. the test pin will sink about 10ma under these conditions. caution: in the lamp test mode, the segments have a constant dc voltage (no square-wave). this may burn the lcd display if maintained for extended periods. - + - + c int r int v int in hi v in in lo v cm (common mode voltage) (v+ - v-)/2 integrator output with in lo too close to positive supply rail (negative input) v+ in lo v- az int. deint. normal integrator output waveform (negative input) v+ in lo v- az int. deint. figure 96. common mode voltage consideration hi7131/33 v+ bp test 21 37 to lcd backplane to lcd decimal point 1m w figure 97. simple inverter for fixed decimal point drive hi7131/33 v+ bp test decimal point select cd4070b gnd v+ to lcd decimal points figure 98. exclusive or gate for decimal points and annunciators drive hi7131, hi7133
3-1840 component selection integrating resistors and capacitors (r int , c int ): a guide- line to achieving the best performance from an integrating a/d converter is to try to reduce the value of r int , increase the value of c int , while having the highest possible voltage swing at the output of the integrator. this will reduce the sen- sitivity of the circuit to noise and leakage currents. in addition to these guidelines the circuit limitations should also be con- sidered. to determine r int , the imposed circuit limitation is the max- imum output drive current of the buffer ampli?er (see figure 5) while maintaining its linearity. this current for the buffer ampli?er is about 1 m a. the r int resistor can be calculated from the expression: the standard optimum values for r int are 180k w for 200mv full scale and 1.8m w for 2v full scale. type of resistor and its absolute value is not critical to the accuracy of conversion, as was discussed previously. the integrating capacitor should be selected to yield the maximum allowable voltage range to the integrator output (int pin). the maximum allowable range does not saturate the integrator output. the integrator output can swing up or down to 0.3v from either supply rail and still maintain its lin- earity. a nominal 2v maximum range is optimum. the maximum range values are selected in order to leave enough room for all the component and circuit tolerances and for a reason- able common mode voltage range. the c int value can now be calculated as: where t int depends on clock frequency and was discussed before and i int is expressed as: for 48khz nominal oscillator frequency (12khz clock internal frequency), r int equals 180k w for 1.8m w for the above mentioned swing, the optimum value for c int is 0.047 m f. an additional requirement of the integrating capacitor is to choose low dielectric absorption. this will minimize the con- verters rollover, linearity and gain error. furthermore, the integrating capacitor should also have low leakage current. different types of capacitors are adequate for this applica- tion; polypropylene capacitors provide undetectable errors at reasonable cost and size. the absolute value of c int does not have any effect on accuracy. auto-zero capacitor (c az ) the value of the auto-zero capacitor has some in?uence on the noise of the converter. a larger value c az has less sensi- tivity to noise. for 200mv full scale (resolution of 100 m v), where noise is important, a 0.47 m f or greater is recom- mended. on the 2v full scale, (resolution of 1mv), a 0.047 m f capacitor is adequate for low noise. the auto-zero capacitor should be a low leakage type to hold the voltage during conversion cycle. a mylar or polypropylene capacitor is recommended for c az . reference capacitor (c ref ) as discussed earlier, the input to the integrator during the deintegrate phase is the voltage at the reference capacitor. the sources of error related to the reference capacitor are stray capacitances at the c ref terminals, and the leakage currents. where a large common mode voltage exists for v ref , the stray capacitances increase the rollover error by absorbing or pumping charge onto c ref when positive or negative inputs are measured. leakage of the capacitor itself or leakages through circuit boards will drop the voltage across c ref and cause gain and rollover errors. the circuit boards should be designed to minimize stray capacitances and should be well cleaned to reduce leakage currents. a 0.1 m f capacitor for c ref should work properly for most applications. when common mode voltage exists or at higher temperatures (where device leakage currents increase) a 1.0 m f reference capacitor is recommended to reduce errors. the c ref capacitor can be any low leakage type, a mylar capacitor is adequate. those applications which have variable reference voltage should also use a low dielectric absorption capacitor such as polypropylene, for example, a ratiometric measurement of resistance. oscillator components when an rc type of oscillator is desired, the oscillator frequency is approximately expressed by: , (r in ohms and c in farads), where r > 50k w and c > 50pf. for 40khz frequency which gives 2.5 readings per second, use 100k and 100pf or use 180k w and 50pf for lower power loss. there is a typical variation of about 5% between oscillator frequencies of different parts. the oscillator frequency will decrease 1% for each 25 o c rise. for those applications in which normal mode rejection of 60hz or 50hz line frequency is critical, a crystal or a precision external oscillator should be used. reference voltage selection for a full scale reading the input signal is required to be twice the reference voltage. to be more precise, the full scale reading ( 1999) takes place when the input is 1.999 times the v ref .v ref is the potential difference between ref hi and ref lo inputs. thus, for the nominal 200mv and 2v ranges, v ref should be 100mv and 1v respectively. r int v in full scale () 1 m a ----------------------------------------- = c int t int i int v intmax ------------------------- - , = i int v in full scale () r int ----------------------------------------- . = f osc 0.45 rc ----------- = hi7131, hi7133
3-1841 in many applications where the a/d is connected to a trans- ducer, there will exist a scale factor other than unity between the input voltage and the digital reading. for instance, in a weighing system, the designer might like to have a full scale reading when the voltage from the transducer is 0.682v. instead of dividing the input down to 200.0mv, the designer should use the input voltage directly and adjust the v ref for 0.341v. suitable values for integrating resistor and capacitor would be 620k w and 0.047 m f. this makes the system slightly quieter and also avoids a divider network on the input. the on-chip voltage reference (v+ - v common ) is normally used to provide the converter reference voltage. however, some applications may desire to use an external reference generator. various possible schemes exist for reference volt- age settings. figure 11 shows the normal way of using on- chip reference and also a way of using external reference. the value of resistors on both circuit depends on the con- verter input voltage range. refer to typical applications section for various schemes. typical applications the hi7131 and hi7133 a/d converters may be used in a wide variety of con?gurations. the following application circuits show some of the possibilities, and serves to illus- trate the exceptional versatility of these devices. the following application notes contain very useful informa- tion on understanding and applying these parts and are available from intersil corporation. application notes note # description answerfax doc. # an016 selecting a/d converters 9016 an017 the integrating a/d converter 9017 an018 dos and donts of applying a/d converters 9018 an032 understanding the auto-zero and common mode performance of the icl7136/7/9 family 9032 an052 tips for using single chip 3 1 / 2 digit a/d converters 9052 hi7131/33 v+ ref hi ref lo common see typical applications section for resistance values for different ranges. v+ hi7131/33 v+ ref hi ref lo common v+ icl8069 1.2v reference 27k 20k w figure 99. hi7131 typical reference circuits hi7131, hi7133
3-1842 typical applications figure 100. hi7131 and hi7133 using the internal reference figure 101. hi7131 and hi7133 with an external band-gap reference (1.2v type) figure 102. recommended component values for 2.000v full-scale, 3 readings/sec figure 103. hi7131 and hi7133 operated from single +5v supply 28 40 39 38 37 36 35 34 33 32 31 30 29 27 26 25 24 23 22 21 osc 1 osc 2 osc 3 test ref hi ref lo c ref c ref common in hi in lo a-z buff int v - g2 c3 a3 g3 bp/gnd 50pf to pin 1 set v ref = 100mv 0.1 m f 0.01 m f 1m w 180k w 20k w 220k w in + - 9v 180k w 0.047 m f 0.47 m f to backplane 0v to display values shown are for 200mv full-scale, 3 readings/sec., ?oating supply voltage (9v battery). 28 40 39 38 37 36 35 34 33 32 31 30 29 27 26 25 24 23 22 21 osc 1 osc 2 osc 3 test ref hi ref lo c ref c ref common in hi in lo a-z buff int v- g2 c3 a3 g3 bp/gnd 50pf to pin 1 set v ref = 100mv 0.1 m f 0.01 m f 1m w 560k w 20k w 180k w in + 180k w 0.15 m f 0.47 m f to backplane 0v to display in lo is tied to supply gnd establishing the correct common-mode voltage. common acts as a pre-regulator for the reference. values shown are for 1 reading/sec. 27k w 1.2v (icl8069) v - v+ 28 40 39 38 37 36 35 34 33 32 31 30 29 27 26 25 24 23 22 21 osc 1 osc 2 osc 3 test ref hi ref lo c ref c ref common in hi in lo a-z buff int v - g2 c3 a3 g3 bp/gnd 50pf to pin 1 set v ref = 1v 0.1 m f 0.01 m f 1m w 180k w 250k w 240k w in + - 1.8m w 0.047 m f 0.47 m f to backplane 0v to display for 1 reading/sec., change c int , r osc to values of figure 12. v+ v - 28 40 39 38 37 36 35 34 33 32 31 30 29 27 26 25 24 23 22 21 osc 1 osc 2 osc 3 test ref hi ref lo c ref c ref common in hi in lo a-z buff int v - g2 c3 a3 g3 bp/gnd 50pf to pin 1 set v ref = 100mv 0.1 m f 0.01 m f 1m w 180k w 20k w 180k w in + - 180k w 0.047 m f 0.47 m f to backplane 0v to display an external reference must be used in this application, since the voltage between v+ and v- is insuf?cient for correct operation of the internal reference. common holds the in lo almost at the middle of the supply, ? 2.7v. 27k w 1.2v (icl8069) +5v hi7131, hi7133
3-1843 figure 104a. hi7131 and hi7133 measuring ratiometric values of quad load cell figure 104b. circuit for developing underrange and overrange signals from hi7133 outputs figure 104. typical applications (continued) 28 40 39 38 37 36 35 34 33 32 31 30 29 27 26 25 24 23 22 21 osc 1 osc 2 osc 3 test ref hi ref lo c ref c ref common in hi in lo a-z buff int v - g2 c3 a3 g3 bp/gnd 50pf to pin 1 0.1 m f 180k w c int 0.47 m f to to display the resistor values within the bridge are determined by the desired sensitivity. r int v+ backplane 0v 13 1 2 3 4 5 6 7 8 9 10 11 12 14 15 16 17 18 19 20 v+ d1 c1 b1 a1 f1 g1 e1 d2 c2 b2 a2 f2 e2 d3 b3 f3 e3 ab4 pol 28 40 39 38 37 36 35 34 33 32 31 30 29 27 26 25 24 23 22 21 osc 1 osc 2 osc 3 test ref hi ref lo c ref c ref common in hi in lo a-z buff int v - g2 c3 a3 g3 gnd o /range u /range cd4023 or 74c10 lm339 to logic v cc +5v v- 33k w 12k w the lm339 is required to ensure logic compatibility with heavy dis- play loading. + + + + - - - - hi7131, hi7133
3-1844 figure 105a. hi7131 and hi7133 used as a digital centigrade thermometer figure 105b. ac to dc converter and hi7133 for rms display figure 105. typical applications (continued) 28 40 39 38 37 36 35 34 33 32 31 30 29 27 26 25 24 23 22 21 osc 1 osc 2 osc 3 test ref hi ref lo c ref c ref common in hi in lo a-z buff int v - g2 c3 a3 g3 bp/gnd 50pf to pin 1 0.1 m f 0.01 m f 180k w 100k w 1m w 9v 390k w 0.047 m f 0.47 m f to backplane 0v to display a silicon diode-connected transistor has a temperature coef?cient of about -2mv/ o c. calibration is achieved by placing the sensing transistor in ice water and adjusting the zeroing potentiome- ter for a 000.0 reading. the sensor should then be placed in boiling water and the scale-factor potentiometer adjusted for a 100.0 reading. see ad590 data sheets for alternative circuits. scale factor adjust 200k w 470k w 100k w silicon npn mps 3764 or similar zero adjust 28 40 39 38 37 36 35 34 33 32 31 30 29 27 26 25 24 23 22 21 osc 1 osc 2 osc 3 test ref hi ref lo c ref c ref common in hi in lo a-z buff int v - g2 c3 a3 g3 gnd 50pf to pin 1 scale factor adjust (v ref > 100mv for ac to rms) 0.1 m f 1 m f 2.2m w 180k w 20k w 180k w 180k w 0.047 m f 0.47 m f to display 100k w 1 m f 1 m f 10k w 10k w 1 m f 470k w 10 m f 10 m f 100pf (for optimum band width) 0.22 m f - + +5v ac in -5v 4.3k hi7131, hi7133
3-1845 figure 106. ac to dc converter with hi7131 and hi7133 figure 107. circuit for developing underrange and overrange signals from hi7131 outputs typical applications (continued) 28 40 39 38 37 36 35 34 33 32 31 30 29 27 26 25 24 23 22 21 osc 1 osc 2 osc 3 test ref hi ref lo c ref c ref common in hi in lo a-z buff int v- g2 c3 a3 g3 bp/gnd 50pf to pin 1 0.1 m f 180k w 20k w 220k w 180k w 0.047 m f 0.47 m f to backplane 0v to display test is used as a common-mode reference level to ensure compatibility with most op amps. 10 m f 9v 10 m f 470k w 1 m f 4.3k w 100pf (for optimum bandwidth) 1 m f 10k w 10k w 1n914 1 m f 0.22 m f 5 m f icl7611 2.2m w + - 100k w ac in scale factor adjust (v ref = 100mv for ac to rms) 13 1 2 3 4 5 6 7 8 9 10 11 12 14 15 16 17 18 19 20 v3 d1 c1 b1 a1 f1 g1 e1 d2 c2 b2 a2 f2 e2 d3 b3 f3 e3 ab4 pol 28 40 39 38 37 36 35 34 33 32 31 30 29 27 26 25 24 23 22 21 osc 1 osc 2 osc 3 test ref hi ref lo c ref c ref common in hi in lo a-z buff int v - g2 c3 a3 g3 bp o /range u /range cd4023 or 74c10 cd4077 to logic v cc v+ to logic gnd v- hi7131, hi7133
3-1846 all intersil semiconductor products are manufactured, assembled and tested under iso9000 quality systems certi?cation. intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design and/o r speci?cations at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of p atents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see web site http://www.intersil.com die characteristics die dimensions: 127 mils x 149 mils metallization: type: al thickness: 10k ? 1k ? passivation: type: psg nitride thickness: 15k ? 3k ? worst case current density: 9.1 x 10 4 a/cm 2 metallization mask layout hi7131, hi7133 a 2 (12) (37) test (39) osc 2 (40) osc 1 (2) d 1 (4) b 1 (27) int (28) buff (33) c ref - a 1 (5) f 1 (6) g 1 (7) e 1 (8) d 2 (9) c 2 (10) b 2 (11) f 2 (13) e 2 (14) b 3 (16) d 3 (15) f 3 (17) e 3 (18) ab 4 (19) pol (20) bp/gnd (21) g 3 (22) a 3 (23) c 3 (24) g 2 (25) v- (26) (29) a/z (30) in lo (31) in hi (32) comm (34) c ref + (35) ref (36) ref lo hi (38) osc 3 (1) v+ (3) c 1 hi7131, hi7133

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